a) Field of the Invention
The present invention relates to a semiconductor device manufacture method and a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having capacitors and MISFETs and its manufacture method.
b) Description of the Related Art
A conventional method of manufacturing a semiconductor device having complementary MOS transistors (CMOS transistors) and capacitors will be described.
As shown in FIG. 11A, the surface of a p-type silicon substrate 100 has element isolation structures 101 to define active regions. One active region is located in an n-type well 102. A gate oxide film 103 is formed on the surface of the active region. An n-type high impurity concentration polysilicon film 104 is deposited on the gate oxide film 103.
As shown in FIG. 11B, an SiO.sub.2 film is deposited on the n-type high impurity concentration polysilicon film 104, and partially etched to leave a capacitor dielectric film 105 on the element isolation structure 101.
As shown in FIG. 11C, another n-type high impurity concentration polysilicon film 106 is deposited on the n-type high impurity concentration polysilicon film 104, covering the capacitor dielectric film 105. On the surface of the n-type high impurity concentration polysilicon film 106, the area where a capacitor upper electrode is formed and the area where gate electrodes of a MISFET are formed, are covered with a resist pattern 107. By using the resist pattern as a mask, the silicon films are partially etched.
FIG. 11D shows the substrate after the silicon films were etched. In the area where the capacitor is formed, an upper electrode 106a of the n-type high impurity concentration polysilicon film 106 corresponding to the resist pattern 107 is left. A lower electrode 104a of the n-type high impurity concentration polysilicon film 104 is left under the capacitor dielectric film 105 which served as an etching mask. In the above manner, a capacitor 108 is formed including the lower electrode 104a, capacitor dielectric film 105, and upper electrode 106a.
In each active region, a gate electrode 107 is formed having a lamination structure of the n-type high impurity concentration polysilicon films 104 and 106.
As shown in FIG. 11E, p-type impurities are doped in both side regions of the gate electrode 107 in the n-type well 102 to form source/drain regions 109, whereas n-type impurities are doped in both side regions of the gate electrode 107 in the active region not formed with the n-type well 102 to form source/drain regions 110. In the above manner, a p-channel MISFET 111 is formed in the n-type well 102, and n-channel MISFET 112 is formed in a surface layer of the p-type silicon substrate 100.
If a natural silicon oxide film is formed at the interface between the n-type high impurity concentration polysilicon films 104 and 106, this natural silicon oxide film functions as an etching stopper layer during the process shown in FIG. 11C and the lower n-type high impurity concentration polysilicon film 104 is left unetched. In order to avoid this, prior to etching the n-type high impurity concentration polysilicon film 106, the surface of the n-type high impurity concentration polysilicon film 104 is cleaned with hydrofluoric acid containing etchant.
However, the surface of the capacitor dielectric film 105 is partially etched slightly during this cleaning, and its thickness changes. A change in the thickness of the capacitor dielectric film 105 results in a variation of capacitances of the capacitor.
In order to reduce a voltage dependency of the capacitance, it is preferable to increase the impurity concentration of the lower and upper electrodes 104a and 106a. In the conventional process of FIG. 11B, the capacitor lower electrode and the lower part of each gate electrode are deposited at the same time and n-type impurities are doped. Therefore, the gate electrodes 107 of the p- and n-channel MISFETs 111 and 112 both have n-type conductivity. It is therefore difficult to constitute a dual gate CMOS circuit having a p-type gate electrode of a p-channel MISFET and an n-type gate electrode of an n-channel MISFET.
The upper electrode 106a and an upper part of each gate electrode 107 are formed by the same process shown in FIG. 11C. Therefore, if the impurity concentration of the upper electrode 106a is made high, the impurity concentration of the upper part of the gate electrode 107 also becomes high. If the impurity concentration is high, silicification with metal becomes difficult.
It is also known that as the impurity concentration becomes high, crystal grains of silicon become large. If the crystal grains of a polysilicon film are large, channeling becomes likely to occur during ion implantation. Therefore, the gate electrode 107 becomes unsuitable for using as a mask when ions are implanted to form source/drain regions.